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The three basic and original HDI processes are laser drilling laminate (Finstrate) and flexible materials (microwiring), photodielectrics with SLC and plasma-etching polyimide (Dycostrate). These and the other 18 HDI processes have been integrated into standard printed circuit manufacturing flows. There is no standard way to organize these processes, but the method of IVH formulation is the most unique characteristic of each process and will be used for this purpose.

Photo-Via Technologies 1,2 23.1.1 IBSS-AAP10 System. The Interpenetrating Polymer Network Build-Up Structure System (IBSS) is a new photodielectric. This photo-imageable dielectric (PID) is a proprietary photodielectric developed by Ibiden of Japan. It complements Ibiden s older epoxy type of photo-redistribution layer technology, IP-10. 23.3.1.1.1 Structure. IBSS is specifically formulated for integrated circuit and flip-chip packages and has a high Tg and flexibility. The bismalene-triazine(BT) core also provides hightemperature resistance. A typical IBSS structure and its features are illustrated in Fig. 23.2. 23.3.1.1.2 Manufacturing Process. IBSS is a liquid system applied by roller coater to a rigid core, typically BT. The coating is cured and photodeveloping creates the vias. The IBSS requires an aggressive swell-and-etch because of the higher-temperature nature of the photo-dielectric (PD). The metallization is fully additive copper, also proprietary to Ibiden.

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The power supply for ELID is used to control the dressing current, voltage and pulse width of the dressing process The metal-bonded wheel is made into the positive pole through the application of a brush smoothly contacting the wheel shaft, and the electrode is made into the negative pole In the small clearance between the positive and negative poles (01-03 mm), electrolysis occurs through the supply of the grinding fluid and an electrical current

The imaging for additive metalization uses a permanent dry-film photoresist For additional layers of dielectric, an adhesion promoter is applied to the surface copper Figure 233 outlines the IBSS process 23312 Surface Laminar Circuits SLC technology was the first of the PID microvia, build-up technologies to reach the interconnect market in high volume Development of SLC technology began during the late 1980s at IBM (Yasu, Japan), and the first product was introduced in 19901 The first flip-chip, direct-chip-attach (FC/DCA) product employing SLC technology was shipped from Yasu in 1992, and in 1995 IBM Endicott, New York, shipped its first printed wiring boards that utilized SLC technology2 Used by many original equipment manufacturers (OEMs) in Japan, the SLC process provided the high-density interconnect technology for Sony s first digital Camcorder, the DCR-PC7, seen in Fig 234.

This eight-layer build-up structure had two SLC layers on each side of a four-layer core The assembly density of this was over 612 pins per sq in due to the wall-to-wall 05 mm pitch chip scale package (CSP) used3 The most suitable photosensitive dielectric was the photo-imageable solder masks, due to their proven compatibility with printed circuit assembly processes, ability to withstand exposure to service environments, and possession of the necessary via-imaging characteristics SLC technology was originally developed and implemented with a liquid PID solder mask applied by curtain coating In 1995, it was also qualified with a dry-film PID with virtually identical electrical properties The dry-film version did not require the extensive surface grinding processes that the liquid PID process required PID technology is based on photoimageable polymeric systems to form blind microvias in dielectric material between layers of circuitry.

The use of PIDs allows all microvias on a panel to be formed simultaneously, with no incremental-per-via cost Its use is particularly advantageous on applications with high densities of vias (eg, more than 50,000 on an 18 in 24 in panel)..

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